Datasheet

47
XMEGA A3U [DATASHEET]
Atmel-8386D-AVR-ATxmega64A3U-128A3U-192A3U-256A3U–03/2014
Figure 28-1. ADC overview.
Two inputs can be sampled simultaneously as both the ADC and the gain stage include sample and hold circuits, and the
gain stage has 1x gain setting.
Four inputs can be sampled within 1.5µs without any intervention by the application.
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.5µs
for 12-bit to 2.5µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when
the result is represented as a signed integer (signed 16-bit number).
PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB, respectively.
CH1 Result
CH0 Result
CH2 Result
Compare
<
>
Threshold
(Int Req)
Internal 1.00V
Internal VCC/1.6V
AREFA
AREFB
V
INP
V
INN
Internal
signals
Internal VCC/2
Internal
signals
CH3 Result
ADC0
ADC7
ADC4
ADC7
ADC0
ADC3
•
•
•
Int. signals
Int. signals
Reference
Voltage
½x - 64x
•
•
•
•
•
•
ADC0
ADC11
•
•
•