Datasheet

8
[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET]
8067O–AVR–06/2013
7. AVR CPU
7.1 Features
 8/16-bit high performance AVR RISC Architecture
 138 instructions
 Hardware multiplier
 32x8-bit registers directly connected to the ALU
 Stack in SRAM
 Stack Pointer accessible in I/O memory space
 Direct addressing of up to 16M Bytes of program and data memory
 True 16/24-bit access to 16/24-bit I/O registers
 Support for 8-, 16- and 32-bit Arithmetic
 Configuration Change Protection of system critical features
7.2 Overview
All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and
perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the
program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable
Multilevel Interrupt Controller” on page 29.
7.3 Architectural Overview
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories
and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to
be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr.