Datasheet
3
[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET]
8067O–AVR–06/2013
2. Pinout/Block Diagram
Figure 2-1. Block diagram and pinout
Notes: 1. For full details on pinout and pin functions refer to “Pinout and Pin Functions” on page 55.
2. VCC/GND on pin 83/84 are swapped compared to other VCC/GND to allow easier routing of GND to 32kHz crystal.
INDEX CORNER
PA6
PA7
GND
AVCC
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
GND
VCC
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
GND
VCC
PD0
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PD1
PD2
PD3
PD4
PD5
PD6
PD7
GND
VCC
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
GND
VCC
PF0
PF1
PF2
PF3
PF4
PF5
PK0
VCC
GND
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
VCC
GND
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
VCC
GND
PF7
PF6
PA5
PA4
PA3
PA2
PA1
PA0
AVCC
GND
PR1
PR0
RESET/PDI
PDI
PQ3
PQ2
PQ1
PQ0
GND
VCC
PK7
PK6
PK5
PK4
PK3
PK2
PK1
FLASH
RAM
E
2
PROM
DMA
Interrupt Controlle r
OCD
External Bus Interface
ADC A
ADC B
DAC B
DAC A
AC A0
AC A1
AC B0
AC B1
Port
A
Port
B
Event System ctrl
Port K
Port J
Port H
Port
Q
Port R
Power
Contro l
Reset
Contro l
Watchdog
OSC/CLK
Contro l
BOD POR
RTC
EVENT ROUTING NETWORK
DATA BU
S
DATA BU
S
VREF
TEMP
Port C
CPU
T/C0:1
USART0:1
TWI
SPI
Port FPort EPort D
T/C0:1
USART0/1
TWI
SPI
T/C0:1
USART0:1
TWI
SPI
T/C0:1
USART0:1
TWI
SPI