Datasheet

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[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET]
8067O–AVR–06/2013
Table 8-3. Number of Bytes and Pages in the EEPROM.
8.14.1 I/O Memory
All peripherals and modules are addressable through I/O memory locations in the data memory space. All I/O memory
locations can be accessed by the Load (LD/LDS/LDD) and Store (ST/STS/STD) instructions, transferring data between
the 32 general purpose registers in the CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. The
value of single bits can be checked by using the SBIS and SBIC instructions on these registers.
The I/O memory address for all peripherals and modules in XMEGA A1 is shown in the “Peripheral Module Address Map”
on page 62.
Device EEPROM Page Size E2BYTE E2PAGE No of pages
Size bytes
ATxmega64A1 2 KB 32 ADDR[4:0] ADDR[10:5] 64
ATxmega128A1 2 KB 32 ADDR[4:0 ADDR[10:5] 64