Datasheet

108
[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET]
8067O–AVR–06/2013
 ±200 LSB for Sample and Hold mode
Problem fix/Workaround
None, avoid using a voltage reference above 2.4V.
4. ADC gain stage output range is limited to 2.4 V
The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential input will only give cor-
rect output when below 2.4 V/gain. For the available gain settings, this gives a differential input range of:
Problem fix/Workaround
Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a correct result, or keep
ADC voltage reference below 2.4 V.
5. The ADC has up to ±2 LSB inaccuracy
The ADC will have up to ±2 LSB inaccuracy, visible as a saw-tooth pattern on the input voltage/ output value trans-
fer function of the ADC. The inaccuracy increases with increasing voltage reference reaching ±2 LSB with 3V
reference.
Problem fix/Workaround
None, the actual ADC resolution will be reduced with up to ±2 LSB.
6. TWI, a general address call will match independent of the R/W-bit value
When the TWI is in Slave mode and a general address call is issued on the bus, the TWI Slave will get an address
match regardless of the R/W-bit (ADDR[0] bit) value in the Slave Address Register.
Problem fix/Workaround
Use software to check the R/W-bit on general call address match.
– 1x gain: 2.4 V
– 2x gain: 1.2 V
– 4x gain: 0.6 V
– 8x gain: 300 mV
– 16x gain: 150 mV
– 32x gain: 75 mV
– 64x gain: 38 mV