Datasheet

56
[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET]
8067O–AVR–06/2013
30.1.5 Timer/Counter and AWEX functions
30.1.6 Communication functions
30.1.7 Oscillators, Clock and Event
CLK SDRAM Clock (SDRAM)
DQM Data Mask Signal/Output Enable (SDRAM)
RAS Row Access Strobe (SDRAM)
2P 2 Port Interface
3P 3 Port Interface
OCnx Output Compare Channel x for Timer/Counter n
OCnx Inverted Output Compare Channel x for Timer/Counter n
OCnxLS Output Compare Channel x Low Side for Timer/Counter n
OCnxHS Output Compare Channel x High Side for Timer/Counter n
SCL Serial Clock for TWI
SDA Serial Data for TWI
SCLIN Serial Clock In for TWI when external driver interface is enabled
SCLOUT Serial Clock Out for TWI when external driver interface is enabled
SDAIN Serial Data In for TWI when external driver interface is enabled
SDAOUT Serial Data Out for TWI when external driver interface is enabled
XCKn Transfer Clock for USART n
RXDn Receiver Data for USART n
TXDn Transmitter Data for USART n
SS Slave Select for SPI
MOSI Master Out Slave In for SPI
MISO Master In Slave Out for SPI
SCK Serial Clock for SPI
n Timer Oscillator pin n
XTALn Input/Output for inverting Oscillator pin n
CLKOUT Peripheral Clock Output
EVOUT Event Channel 0 Output