Datasheet

i
32142D–06/2013
ATUC64/128/256L3/4U
Table of Contents
Features ..................................................................................................... 1
1 Description ............................................................................................... 3
2 Overview ................................................................................................... 5
2.1 Block Diagram ...................................................................................................5
2.2 Configuration Summary .....................................................................................6
3 Package and Pinout ................................................................................. 7
3.1 Package .............................................................................................................7
3.2 See Section 3.3 for a description of the various peripheral signals. ................12
3.3 Signal Descriptions ..........................................................................................15
3.4 I/O Line Considerations ...................................................................................18
4 Processor and Architecture .................................................................. 21
4.1 Features ..........................................................................................................21
4.2 AVR32 Architecture .........................................................................................21
4.3 The AVR32UC CPU ........................................................................................22
4.4 Programming Model ........................................................................................26
4.5 Exceptions and Interrupts ................................................................................30
5 Memories ................................................................................................ 35
5.1 Embedded Memories ......................................................................................35
5.2 Physical Memory Map .....................................................................................35
5.3 Peripheral Address Map ..................................................................................36
5.4 CPU Local Bus Mapping .................................................................................37
6 Supply and Startup Considerations ..................................................... 39
6.1 Supply Considerations .....................................................................................39
6.2 Startup Considerations ....................................................................................44
7 Peripheral DMA Controller (PDCA) ...................................................... 45
7.1 Features ..........................................................................................................45
7.2 Overview ..........................................................................................................45
7.3 Block Diagram .................................................................................................46
7.4 Product Dependencies ....................................................................................46
7.5 Functional Description .....................................................................................47
7.6 Performance Monitors .....................................................................................49
7.7 User Interface ..................................................................................................51