Datasheet

953
32142D–06/2013
ATUC64/128/256L3/4U
39. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
39.1 Rev. D – 06/2013
39.2 Rev. C – 01/2012
39.3 Rev. B – 12/2011
39.4 Rev. A – 12/2011
1. Updated the datasheet with a new ATmel blue logo and the last page.
2. Added Flash errata.
1. Description: DFLL frequency is 20 to 150MHz, not 40 to 150MHz.
2. Block Diagram: GCLK_IN is input, not output. CAT SMP corrected from I/O to output. SPI
NPCS corrected from output to I/O.
3, Package and Pinout: EXTINT0 in Signal Descriptions table is NMI.
4, Supply and Startup Considerations: In 1.8V single supply mode figure, the input voltage is
1.62-1.98V, not 1.98-3.6V. “On system start-up, the DFLL is disabled” is replaced by “On
system start-up, all high-speed clocks are disabled”.
5, ADCIFB: PRND signal removed from block diagram.
6, Electrical Charateristics: Added 64-pin package information to I/O Pin Characteristics tables
and Digital Clock Characteristics table.
7, Mechanical Characteristics: QFN48 Package Drawing updated. Note that the package drawing
for QFN48 is correct in datasheet rev A, but wrong in rev B. Added notes to package drawings.
8. Summary: Removed Programming and Debugging chapter, added Processor and Architecture
chapter.
1. JTAG Data Registers subchapter added in the Programming and Debugging chapter,
containing JTAG IDs.
1. Initial revision.