Datasheet

924
32142D–06/2013
ATUC64/128/256L3/4U
Figure 35-12. USART in SPI Slave Mode with (CPOL= CPHA= 0) or (CPOL= CPHA= 1)
Figure 35-13. USART in SPI Slave Mode, NPCS Timing
Notes: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
2. Where:
USPI10 USPI11
MISO
SPCK
MOSI
USPI9
USPI14
USPI12
USPI15
USPI13
NSS
SPCK, CPOL=0
SPCK, CPOL=1
Table 35-42. USART in SPI mode Timing, Slave Mode
(1)
Symbol Parameter Conditions Min Max Units
USPI6 SPCK falling to MISO delay
V
VDDIO
from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
37.3
ns
USPI7 MOSI setup time before SPCK rises
2.6 + t
SAMPLE
(2)
+
t
CLK_USART
USPI8 MOSI hold time after SPCK rises 0
USPI9 SPCK rising to MISO delay 37.0
USPI10 MOSI setup time before SPCK falls
2.6 + t
SAMPLE
(2)
+
t
CLK_USART
USPI11 MOSI hold time after SPCK falls 0
USPI12 NSS setup time before SPCK rises 27.2
USPI13 NSS hold time after SPCK falls 0
USPI14 NSS setup time before SPCK falls 27.2
USPI15 NSS hold time after SPCK rises 0
t
SAMPLE
t
SPCK
t
SPCK
2 t
CLKUSART

------------------------------------
1
2
---+


t
CLKUSART
–=