Datasheet

922
32142D–06/2013
ATUC64/128/256L3/4U
35.10.3 USART in SPI Mode Timing
35.10.3.1 Master mode
Figure 35-9. USART in SPI Master Mode with (CPOL= CPHA= 0) or (CPOL= CPHA= 1)
Figure 35-10. USART in SPI Master Mode with (CPOL= 0 and CPHA= 1) or (CPOL= 1 and
CPHA= 0)
Notes: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
2. Where:
USPI0 USPI1
MISO
SPCK
MOSI
USPI2
USPI3 USPI4
MISO
SPCK
MOSI
USPI5
Table 35-41. USART in SPI Mode Timing, Master Mode
(1)
Symbol Parameter Conditions Min Max Units
USPI0 MISO setup time before SPCK rises
V
VDDIO
from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
28.7 + t
SAMPLE
(2)
ns
USPI1 MISO hold time after SPCK rises 0
USPI2 SPCK rising to MOSI delay 16.5
USPI3 MISO setup time before SPCK falls 25.8 + t
SAMPLE
(2)
USPI4 MISO hold time after SPCK falls 0
USPI5 SPCK falling to MOSI delay 21.19
t
SAMPLE
t
SPCK
t
SPCK
2 t
CLKUSART

------------------------------------
1
2
---


t
CLKUSART
–=