Datasheet

908
32142D–06/2013
ATUC64/128/256L3/4U
35.6.4 Digital Frequency Locked Loop (DFLL) Characteristics
Notes: 1. Spread Spectrum Generator (SSG) is disabled by writing a zero to the EN bit in the DFLL0SSG register.
2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
3. The FINE and COARSE values are selected by wrirting to the DFLL0VAL.FINE and DFLL0VAL.COARSE field respectively.
Table 35-14. Digital Frequency Locked Loop Characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
OUT
Output frequency
(2)
20 150 MHz
f
REF
Reference frequency
(2)
8 150 kHz
FINE resolution step FINE > 100, all COARSE values
(3)
0.38 %
Frequency drift over voltage
and temperature
Open loop mode
See Figure
35-4
Accuracy
(2)
FINE lock, f
REF
= 32kHz, SSG disabled 0.1 0.5
%
ACCURATE lock, f
REF
= 32kHz, dither clk
RCSYS/2, SSG disabled
0.06 0.5
FINE lock, f
REF
= 8-150kHz, SSG
disabled
0.2 1
ACCURATE lock, f
REF
= 8-150kHz,
dither clk RCSYS/2, SSG disabled
0.1 1
I
DFLL
Power consumption 25 µA/MHz
t
STARTUP
Startup time
(2)
Within 90% of final values 100 µs
t
LOCK
Lock time
f
REF
= 32kHz, FINE lock, SSG disabled 8
ms
f
REF
= 32kHz, ACCURATE lock, dithering
clock = RCSYS/2, SSG disabled
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