Datasheet

898
32142D–06/2013
ATUC64/128/256L3/4U
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers
manufactured in the same process technology. These values are not covered by test limits in
production.
35.3 Maximum Clock Frequencies
These parameters are given in the following conditions:
•V
VDDCORE
= 1.62V to 1.98V
• Temperature = -40°C to 85°C
35.4 Power Consumption
The values in Table 35-5 are measured values of power consumption under the following condi-
tions, except where noted:
• Operating conditions, internal core supply (Figure 35-1) - this is the default configuration
–V
VDDIN
= 3.0V
Table 35-3. Supply Rise Rates and Order
(1)
Symbol Parameter
Rise Rate
Min Max Unit Comment
V
VDDIO
DC supply peripheral I/Os 0 2.5 V/µs
V
VDDIN
DC supply peripheral I/Os
and internal regulator
0.002 2.5 V/µs
Slower rise time requires
external power-on reset
circuit.
V
VDDCORE
DC supply core 0 2.5 V/µs
Rise before or at the same
time as VDDIO
V
VDDANA
Analog supply voltage 0 2.5 V/µs
Rise together with
VDDCORE
Table 35-4. Clock Frequencies
Symbol Parameter Description Min Max Units
f
CPU
CPU clock frequency 50
MHz
f
PBA
PBA clock frequency 50
f
PBB
PBB clock frequency 50
f
GCLK0
GCLK0 clock frequency DFLLIF main reference, GCLK0 pin 50
f
GCLK1
GCLK1 clock frequency DFLLIF dithering and SSG reference, GCLK1 pin 50
f
GCLK2
GCLK2 clock frequency AST, GCLK2 pin 20
f
GCLK3
GCLK3 clock frequency PWMA, GCLK3 pin 140
f
GCLK4
GCLK4 clock frequency CAT, ACIFB, GCLK4 pin 50
f
GCLK5
GCLK5 clock frequency GLOC and GCLK5 pin 80
f
GCLK6
GCLK6 clock frequency ABDACB, IISC, and GCLK6 pin 50
f
GCLK7
GCLK7 clock frequency USBC and GCLK7 pin 50
f
GCLK8
GCLK8 clock frequency PLL0 source clock and GCLK8 pin 50
f
GCLK9
GCLK9 clock frequency FREQM, GCLK0-8, GCLK9 pin 150