Datasheet

892
32142D–06/2013
ATUC64/128/256L3/4U
34.6.7.11 HALT
This command tells the CPU to halt code execution for safe programming. If the CPU is not
halted during programming it can start executing partially loaded programs. To halt the proces-
sor, the aWire master should send 0x01 in the data field of the command. After programming the
halting can be released by sending 0x00 in the data field of the command.
34.6.7.12 RESET
This command resets different domains in the part. The aWire master sends a byte with the
reset value. Each bit in the reset value byte corresponds to a reset domain in the chip. If a bit is
set the reset is activated and if a bit is not set the reset is released. The number of reset domains
and their destinations are identical to the resets described in the JTAG data registers chapter
under reset register.
34.6.7.13 SET_GUARD_TIME
Sets the guard time value in the AW, i.e. how long the AW will wait before starting its transfer
after the master has finished.
The guard time can be either 0x00 (128 bit lengths), 0x01 (16 bit lengths), 0x2 (4 bit lengths) or
0x3 (1 bit length).
Table 34-45. HALT Details
Command Details
Command value 0x82
Additional data
0x01 to halt the CPU 0x00 to release the halt and reset the
device.
Possible responses
0x40: ACK (Section 34.6.8.1)
0x41: NACK (Section 34.6.8.2)
Table 34-46. RESET Details
Command Details
Command value 0x83
Additional data
Reset value for each reset domain. The number of reset
domains is part specific.
Possible responses
0x40: ACK (Section 34.6.8.1)
0x41: NACK (Section 34.6.8.2)
Table 34-47. SET_GUARD_TIME Details
Command Details
Command value 0x84
Additional data Guard time
Possible responses
0x40: ACK (Section 34.6.8.1)
0x41: NACK (Section 34.6.8.2)