Datasheet

849
32142D–06/2013
ATUC64/128/256L3/4U
34.3.5 Block Diagram
Figure 34-1.
On-Chip Debug Block Diagram
34.3.6 SAB-based Debug Features
A debugger can control all OCD features by writing OCD registers over the SAB interface. Many
of these do not depend on output on the AUX port, allowing an aWire- or JTAG-based debugger
to be used.
A JTAG-based debugger should connect to the device through a standard 10-pin IDC connector
as described in the AVR32UC Technical Reference Manual.
An aWire-based debugger should connect to the device through the RESET_N pin.
On-Chip Debug
JTAG
Debug PC
Debug
Instruction
CPU
Breakpoints
Program
Trace
Data Trace
Ownership
Trace
WatchpointsTransmit Queue
AUX
JTAG
Internal
SRAM
S
e
r
v
i
c
e
A
c
c
e
s
s
B
u
s
Memory
Service
Unit
HSB Bus Matrix
Memories and
peripherals
aWire
aWire