Datasheet

32142D–06/2013

ATUC64/128/256L3/4U

7.8 Module Configuration

The specific configuration for each PDCA instance is listed in the following tables.The module

bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man-

ager chapter for details.

The PDCA and the peripheral modules communicate through a set of handshake signals. The

following table defines the valid settings for the Peripheral Identifier (PID) in the PDCA Periph-

eral Select Register (PSR). The direction is specified as observed from the memory, so RX

means transfers from peripheral to memory, and TX means from memory to peripheral.

Table 7-6. PDCA Configuration

Feature PDCA

Number of channels 12

Number of performance monitors 1

Table 7-7. PDCA Clocks

Clock Name Description

CLK_PDCA_HSB Clock for the PDCA HSB interface

CLK_PDCA_PB Clock for the PDCA PB interface

Table 7-8. Register Reset Values

PSR CH 0 0

PSR CH 1 1

PSR CH 2 2

PSR CH 3 3

PSR CH 4 4

PSR CH 5 5

PSR CH 6 6

PSR CH 7 7

PSR CH 8 8

PSR CH 9 9

PSR CH 10 10

PSR CH 11 11

VERSION 123

Table 7-9. Peripheral Identity Values

PID Direction Peripheral Instance Peripheral Register

0 RX USART0 RHR

1 RX USART1 RHR

2 RX USART2 RHR