Datasheet

776
32142D–06/2013
ATUC64/128/256L3/4U
In order to use the QMatrix, QTouch group A, or QTouch group B acquisition capabilities, it is
first necessary to set up the pin mode registers (PINMODE0, PINMODE1, and PINMODE2) and
configuration registers (MGCFG0, MGCFG1, TGACFG0, TGACFG1, TGBCFG0, and
TGBCFG1). The module must then be enabled using the CTRL register. In order to initiate
acquisition, it is necessary to perform a write to the Acquisition Initiation and Selection Register
(AISR). The specific value written to AISR determines which type of acquisition will be per-
formed: QMatrix, QTouch group A, or QTouch group B. The CPU can initiate acquisition by
writing to the AISR.
While QMatrix, QTouch group A, or QTouch group B acquisition is in progress, the module col-
lects count values from the sensors and buffers them. Availability of acquired count data is
indicated by the Acquisition Ready (ACREADY) bit in the Status Register (SR). The CPU or the
Peripheral DMA Controller can then read the acquired counts from the ACOUNT register.
Because the CAT module is configured with Peripheral DMA Controller capability that can trans-
fer data from memory to MBLEN and from ACOUNT to memory, the Peripheral DMA Controller
can perform long acquisition sequences and store results in memory without CPU intervention.
31.6.2 Prescaler and Charge Length
Each QTouch acquisition type (autonomous QTouch, QTouch group A, and QTouch group B)
has its own prescaler. Each QTouch prescaler divides down the CLK_CAT clock to an appropri-
ate sampling frequency for its particular acquisition type. Typical frequencies are 1MHz for
QTouch acquisition and 4MHz for QMatrix burst timing control.
Each QTouch prescaler is controlled by the DIV field in the appropriate Configuration Register 0
(ATCFG0, TGACFG0, or TGBCFG0). The QMatrix burst timing prescaler is controlled by the
DIV field in MGCFG0. Each prescaler uses the following formula to generate the sampling clock:
Sampling clock = CLK_CAT / (2(DIV+1))
The capacitive sensor charge length, discharge length, and settle length can be determined for
each acquisition type using the CHLEN, DILEN, and SELEN fields in Configuration Registers 0
and 1. The lengths are specified in terms of prescaler clocks. In addition, the QMatrix Cx dis-
charge length can be determined using the CXDILEN field in MGCFG2.
For QMatrix acquisition, the duration of CHLEN should not be set to the same value as the
period of any periodic signal on any other pin. If the duration of CHLEN is the same as the
period of a signal on another pin, it is likely that the other signal will significantly affect measure-
ments due to stray capacitive coupling. For example, if a 1 MHz signal is generated on another
pin of the chip, then CHLEN should not be 1 microsecond.
For the QMatrix method, burst and capture lengths are set for each (X,Y) pair by writing the
desired length values to the MBLEN register. The write must be done before each X line can
start its acquisition and is indicated by the status bit MBLREQ in the Status Register (SR). A
DMA handshake interface is also connected to this status bit to reduce CPU overhead during
QMatrix acquisitions.
Four burst lengths (BURST0..3) can be written at one time into the MBLEN register. If the cur-
rent configuration uses Y lines larger than Y3 the register has to be written a second time. The
first write to MBLEN specifies the burst length for Y lines 0 to 3 in the BURST0 to BURST3 fields,
respectively. The second write specifies the burst length for Y lines 4 to 7 in fields BURST0 to
BURST3, respectively, and so on.