Datasheet

32142D–06/2013

ATUC64/128/256L3/4U

30.9.5 Interrupt Mask Register

Name:

IMR

Access Type: Read-only

Offset: 0x18

Reset Value: 0x00000000

•WFINTn: Window Mode Interrupt Mask

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

This bit is cleared when the corresponding bit in IDR is written to one.

This bit is set when the corresponding bit in IER is written to one.

•SUTINTn: ACn Startup Time Interrupt Mask

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

This bit is cleared when the corresponding bit in IDR is written to one.

This bit is set when the corresponding bit in IER is written to one.

• ACINTn: ACn Interrupt Mask

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

This bit is cleared when the corresponding bit in IDR is written to one.

This bit is set when the corresponding bit in IER is written to one.

31 30 29 28 27 26 25 24

- - - - WFINT3 WFINT2 WFINT1 WFINT0

23 22 21 20 19 18 17 16

--------

15 14 13 12 11 10 9 8

SUTINT7 ACINT7 SUTINT6 ACINT6 SUTINT5 ACINT5 SUTINT4 ACINT4

76543210

SUTINT3 ACINT3 SUTINT2 ACINT2 SUTINT1 ACINT1 SUTINT0 ACINT0