Datasheet

748
32142D–06/2013
ATUC64/128/256L3/4U
The signal names corresponds to the groups A and B of analog comparators. For normal mode,
the mapping from input signal names in the block diagram to the signal names is given in Table
30-3.
30.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
30.5.1 I/O Lines
The ACIFB pins are multiplexed with other peripherals. The user must first program the I/O Con-
troller to give control of the pins to the ACIFB.
30.5.2 Power Management
If the CPU enters a sleep mode that disables clocks used by the ACIFB, the ACIFB will stop
functioning and resume operation after the system wakes up from sleep mode.
30.5.3 Clocks
The clock for the ACIFB bus interface (CLK_ACIFB) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-
able the ACIFB before disabling the clock, to avoid freezing the ACIFB in an undefined state.
The ACIFB uses a GCLK as clock source for the Analog Comparators. The user must set up this
GCLK at the right frequency. The CLK_ACIFB clock of the interface must be at least 4x the
GCLK frequency used in the comparators. The GCLK is used both for measuring the startup
time of a comparator, and to give a frequency for the comparisons done in Continuous Measure-
ment Mode, see Section 30.6.
Refer to the Electrical Characteristics chapter for GCLK frequency limitations.
ACBPn Positive reference pin for Analog Comparator B n Analog
ACBNn Negative reference pin for Analog Comparator B n Analog
ACREFN Reference Voltage for all comparators selectable for INN Analog
Table 30-3. Signal Name Mapping
Pin Name Channel Number Normal Mode
ACAP0/ACAN0 0 ACP0/ACN0
ACBP0/ACBN0 1 ACP1/ACN1
ACAP1/ACAN1 2 ACP2/ACN2
ACBP1/ACBN1 3 ACP3/ACN3
ACAP2/ACAN2 4 ACP4/ACN4
ACBP2/ACBN2 5 ACP5/ACN5
ACAP3/ACAN3 6 ACP6/ACN6
ACBP3/ACBN3 7 ACP7/ACN7
Table 30-2. I/O Line Description
Pin Name Pin Description Type