Datasheet

744
32142D–06/2013
ATUC64/128/256L3/4U
29.9.17 Channel Status Register
Name:
CHSR
Access Type: Read-only
Offset: 0x48
Reset Value: 0x00000000
• CHn: Channel N Status
0: The corresponding channel is disabled.
1: The corresponding channel is enabled.
A bit in this register is cleared by writing a one to the corresponding bit in Channel Disable Register (CHDR).
A bit in this register is set by writing a one to the corresponding bit in Channel Enable Register (CHER).
The number of available channels is device dependent. Please refer to the Module Configuration section at the end of this
chapter for information regarding how many channels are implemented.
31 30 29 28 27 26 25 24
CH31 CH30 CH29 CH28 CH27 CH26 CH25 CH24
23 22 21 20 19 18 17 16
CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH16
15 14 13 12 11 10 9 8
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0