Datasheet

743
32142D–06/2013
ATUC64/128/256L3/4U
29.9.16 Channel Disable Register
Name:
CHDR
Access Type: Write-only
Offset: 0x44
Reset Value: 0x00000000
• CHn: Channel N Disable
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register disables the corresponding channel.
Warning: If the corresponding channel is disabled during a conversion, or if it is disabled and then re-enabled during a
conversion, its associated data and
its corresponding DRDY and OVRE bits in SR are unpredictable.
The number of available channels is device dependent. Please refer to the Module Configuration section at the end of this
chapter for information regarding how many channels are implemented.
31 30 29 28 27 26 25 24
CH31 CH30 CH29 CH28 CH27 CH26 CH25 CH24
23 22 21 20 19 18 17 16
CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH16
15 14 13 12 11 10 9 8
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0