Datasheet

713
32142D–06/2013
ATUC64/128/256L3/4U
29.4 I/O Lines Description
29.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
29.5.1 I/O Lines
The analog input pins can be multiplexed with I/O Controller lines. The user must make sure the
I/O Controller is configured correctly to allow the ADCIFB access to the AD pins before the
ADCIFB is instructed to start converting data. If the user fails to do this the converted data may
be wrong.
The number of analog inputs is device dependent, please refer to the ADCIFB Module Configu-
ration chapter for the number of available AD inputs on the current device.
The ADVREFP pin must be connected correctly prior to using the ADCIFB. Failing to do so will
result in invalid ADC operation. See the Electrical Characteristics chapter for details.
If the TRIGGER, ADP0, and ADP1 pins are to be used in the application, the user must config-
ure the I/O Controller to assign the needed pins to the ADCIFB function.
29.5.2 Power Management
If the CPU enters a sleep mode that disables clocks used by the ADCIFB, the ADCIFB will stop
functioning and resume operation after the system wakes up from sleep mode.
If the Peripheral Event System is configured to send asynchronous peripheral events to the
ADCIFB and the clock used by the ADCIFB is stopped, a local and temporary clock will automat-
ically be requested so the event can be processed. Refer to Section 29.6.13, Section 29.6.12,
and the Peripheral Event System chapter for details.
Before entering a sleep mode where the clock to the ADCIFB is stopped, make sure the Analog-
to-Digital Converter cell is put in an inactive state. Refer to Section 29.6.13 for more information.
29.5.3 Clocks
The clock for the ADCIFB bus interface (CLK_ADCIFB) is generated by the Power Manager.
This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to
disable the ADCIFB before disabling the clock, to avoid freezing the ADCIFB in an undefined
state.
Table 29-1. I/O Lines Description
Pin Name Description Type
ADVREFP Reference voltage Analog
TRIGGER External trigger Digital
ADP0 Drive Pin 0 for Resistive Touch Screen top channel (Xp) Digital
ADP1 Drive Pin 1 for Resistive Touch Screen right channel (Yp) Digital
AD0-ADn Analog input channels 0 to n Analog