Datasheet

711
32142D–06/2013
ATUC64/128/256L3/4U
29. ADC Interface (ADCIFB)
Rev:1.0.1.1
29.1 Features
Multi-channel Analog-to-Digital Converter with up to 12-bit resolution
Enhanced Resolution Mode
11-bit resolution obtained by interpolating 4 samples
12-bit resolution obtained by interpolating 16 samples
Glueless interface with resistive touch screen panel, allowing
Resistive Touch Screen position measurement
Pen detection and pen loss detection
Integrated enhanced sequencer
ADC Mode
Resistive Touch Screen Mode
Numerous trigger sources
Software
Embedded 16-bit timer for periodic trigger
Pen detect trigger
Continuous trigger
External trigger, rising, falling, or any-edge trigger
Peripheral event trigger
ADC Sleep Mode for low power ADC applications
Programmable ADC timings
Programmable ADC clock
Programmable startup time
29.2 Overview
The ADC Interface (ADCIFB) converts analog input voltages to digital values. The ADCIFB is
based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Converter (ADC).
The conversions extend from 0V to ADVREFP.
The ADCIFB supports 8-bit and 10-bit resolution mode, in addition to enhanced resolution mode
with 11-bit and 12-bit resolution. Conversion results are reported in a common register for all
channels.
The 11-bit and 12-bit resolution modes are obtained by interpolating multiple samples to acquire
better accuracy. For 11-bit mode 4 samples are used, which gives an effective sample rate of
1/4 of the actual sample frequency. For 12-bit mode 16 samples are used, giving a effective
sample rate of 1/16 of actual. This arrangement allows conversion speed to be traded for better
accuracy.
Conversions can be started for all enabled channels, either by a software trigger, by detection of
a level change on the external trigger pin (TRIGGER), or by an integrated programmable timer.
When the Resistive Touch Screen Mode is enabled, an integrated sequencer automatically con-
figures the pad control signals and performs resistive touch screen conversions.
The ADCIFB also integrates an ADC Sleep Mode, a Pen-Detect Mode, and an Analog Compare
Mode, and connects with one Peripheral DMA Controller channel. These features reduce both
power consumption and processor intervention.