Datasheet

697
32142D–06/2013
ATUC64/128/256L3/4U
28.7.1 Control Register
Name:
CR
Access Type: Read/Write
Offset: 0x00
Reset Value: 0x00000000
• FS: Sampling Frequency
Must be set to the matching data sampling frequency, see Table 28-3.
Note: 1. The actual clock requirement are 11.9952MHz, 23.9904MHz, and 47.9808MHz, but this is
very close to the suggested clock frequencies, and will only result in a very small frequency
shift. This need to be accounted for during testing if comparing to a reference signal.
Notes: 1.
31 30 29 28 27 26 25 24
---- FS
23 22 21 20 19 18 17 16
----- DATAFORMAT
15 14 13 12 11 10 9 8
--------
76543210
SWRST - MONO CMOC ALTUPR - SWAP EN
Table 28-3. Generic Clock Requirements
CR.FS Description GCLK (CR.ALTUPR=1) GCLK (CR.ALTUPR=0)
0 8000Hz sampling frequency 8.0MHz 8.1920MHz
1 11025Hz sampling frequency 12.0MHz
(1)
11.2896MHz
2 12000Hz sampling frequency 12.0MHz 12.2880MHz
3 16000Hz sampling frequency 16.0MHz 16.3840MHz
4 22050Hz sampling frequency 24.0MHz
(1)
22.5792MHz
5 24000Hz sampling frequency 24.0MHz 24.5760MHz
6 32000Hz sampling frequency 32.0MHz 32.7680MHz
7 44100Hz sampling frequency 48.0MHz
(1)
45.1584MHz
8 48000Hz sampling frequency 48.0MHz 49.1520MHz
Other Reserved - -