Datasheet

693
32142D–06/2013
ATUC64/128/256L3/4U
SDR1) before 1/F
S
second, or an underrun will occur, as indicated by the Underrun Interrupt bit
in SR (SR.TXUR). The interrupt bits in SR are cleared by writing a one to the corresponding bit
in the Status Clear Register (SCR).
28.6.12 Frequency Response
Figure Figure 28-4 to Figure 28-7 show the frequency response for the system. The sampling
frequency used is 48kHz, but the response will be the same for other sampling frequencies,
always having the first zero at F
S
.
Figure 28-4. Passband Frequency Response