Datasheet

641
32142D–06/2013
ATUC64/128/256L3/4U
25.8 Module Configuration
The specific configuration for each PWMA instance is listed in the following tables. The module
bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man-
ager chapter for details.
Table 25-4. PWMA Configuration
Feature PWMA
Number of PWM channels 36
Channels supporting incoming peripheral events 0, 6, 8, 9, 11, 14, 19, and 20
PWMA channels with Open Drain mode 21, 27, and 28
Table 25-5. PWMA Clocks
Clock Name Descripton
CLK_PWMA Clock for the PWMA bus interface
GCLK The generic clock used for the PWMA is GCLK3
Table 25-6. Register Reset Values
Register Reset Value
VERSION 0x00000201
PARAMETER 0x00000024