Manualshelf

Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TLLGA 48 (5.5x5.5) 32-Bit 50 MHz I/O number 36
631632633634635636637638639640
637
32142D–06/2013
ATUC64/128/256L3/4U
25.7.14 Channel Event Response Register
Name:
CHERRm
Access Type: Read/Write
Offset: 0x34+m*0x10
Reset Value: 0x00000000
•
CHER: Channel Event Response
0: The increase event will increase the duty cycle value by one in a PWM period for the corresponding channel and the
decrease event will decrease the duty cycle value by one.
1: The increase event will decrease the duty cycle value by one in a PWM period for the corresponding channel and the
decrease event will increase the duty cycle value by one.
The events are taken into account when the common timebase counter reaches its top.
If more than one CHERR register is present, CHERR0 controls channels 31-0 and CHERR1 controls channels 64-32 and so on.
31 30 29 28 27 26 25 24
CHER
23 22 21 20 19 18 17 16
CHER
15 14 13 12 11 10 9 8
CHER
76543210
CHER