Datasheet

564
32142D–06/2013
ATUC64/128/256L3/4U
23.7.2 Power Management
If the CPU enters a sleep mode that disables clocks used by the TWIS, the TWIS will stop func-
tioning and resume operation after the system wakes up from sleep mode. The TWIS is able to
wake the system from sleep mode upon address match, see Section 23.8.8 on page 572.
23.7.3 Clocks
The clock for the TWIS bus interface (CLK_TWIS) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-
able the TWIS before disabling the clock, to avoid freezing the TWIS in an undefined state.
23.7.4 DMA
The TWIS DMA handshake interface is connected to the Peripheral DMA Controller. Using the
TWIS DMA functionality requires the Peripheral DMA Controller to be programmed after setting
up the TWIS.
23.7.5 Interrupts
The TWIS interrupt request lines are connected to the interrupt controller. Using the TWIS inter-
rupts requires the interrupt controller to be programmed first.
23.7.6 Debug Operation
When an external debugger forces the CPU into debug mode, the TWIS continues normal oper-
ation. If the TWIS is configured in a way that requires it to be periodically serviced by the CPU
through interrupts or similar, improper operation or data loss may result during debugging.
23.8 Functional Description
23.8.1 Transfer Format
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must
be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure
23-4 on page 565).
Each transfer begins with a START condition and terminates with a STOP condition (see Figure
23-3).
• A high-to-low transition on the TWD line while TWCK is high defines the START condition.
• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 23-3. START and STOP Conditions
TWD
TWCK
Start Stop