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Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TLLGA 48 (5.5x5.5) 32-Bit 50 MHz I/O number 36
41424344454647484950
50
32142D–06/2013
ATUC64/128/256L3/4U
The registers can also be manually reset by writing a one to the Channel Reset bit in the PCON-
TROL register (PCONTROL.CH0/1RES). The Performance Channel Read/Write Latency
registers (PRLAT0/1 and PWLAT0/1) are saturating when their maximum count value is
reached. The PRLAT0/1 and PWLAT0/1 registers can only be reset by writing a one to the cor-
responding reset bit in PCONTROL (PCONTROL.CH0/1RES).
A counter is enabled by writing a one to the Channel Enable bit in the Performance Control Reg-
ister (PCONTROL.CH0/1EN).