Datasheet

5
32142D–06/2013
ATUC64/128/256L3/4U
2. Overview
2.1 Block Diagram
Figure 2-1. Block Diagram
INTERRUPT
CONTROLLER
ASYNCHRONOUS
TIMER
PERIPHERAL
DMA
CONTROLLER
HSB-PB
BRIDGE B
HSB-PB
BRIDGE A
S
MM M
S
S
M
EXTERNAL INTERRUPT
CONTROLLER
HIGH SPEED
BUS MATRIX
GENERALPURPOSE I/Os
GENERAL PURPOSE I/Os
PA
PB
EXTINT[5..1]
NMI
PA
PB
SPI
DMA
MISO, MOSI
NPCS[3..0]
USART0
USART1
USART2
USART3
DMA
RXD
TXD
CLK
RTS, CTS
WATCHDOG
TIMER
SCK
JTAG
INTERFACE
MCKO
MDO[5..0]
MSEO[1..0]
EVTI_N
TDO
TDI
TMS
CONFIGURATION REGISTERS BUS
256/128/64
KB
FLASH
S
FLASH
CONTROLLER
EVTO_N
AVR32UC CPU
NEXUS
CLASS 2+
OCD
INSTR
INTERFACE
DATA
INTERFACE
MEMORY INTERFACE
LOCAL BUS
32/16 KB
SRAM
MEMORY PROTECTION UNIT
LOCAL BUS
INTERFACE
FREQUENCY METER
PWM CONTROLLER
PWMA[35..0]
TWI MASTER 0
TWI MASTER 1
DMA
TWI SLAVE 0
TWI SLAVE 1
DMA
8-CHANNEL ADC
INTERFACE
DMA
POWER MANAGER
RESET
CONTROLLER
SLEEP
CONTROLLER
CLOCK
CONTROLLER
TCK
aWire
RESET_N
CAPACITIVE TOUCH
MODULE
DMA
AC INTERFACE
ACREFN
ACAN[3..0]
ACBN[3..0]
ACBP[3..0]
ACAP[3..0]
TWCK
TWD
TWALM
TWCK
TWD
TWALM
GLUE LOGIC
CONTROLLER
IN[7..0]
OUT[1..0]
USB 2.0
Interface
8EP
DMA
INTER-IC SOUND
CONTROLLER
TIMER/COUNTER 0
TIMER/COUNTER 1
A[2..0]
B
[
2
.
.
0
]
AUDIO BITSTREAM
DAC
DMA
DAC0, DAC1
DACN0, DACN1
ISCK
IWS
ISDI
ISDO
IMCK
CLK
SAU
S/M
S
D
M
D
P
SYSTEM CONTROL
INTERFACE
GCLK[9..0]
XIN32
XOUT32
OSC32K
RCSYS
X
I
N
0
X
O
U
T
0
OSC0
DFLL
RC32K
RC120M
RC32OUT
PLL
GCLK_IN[2..0]
CSB[16:0]
SMP
CSA[16:0]
SYNC
VDIVEN
DIS
TRIGGER
ADP[1..0]
AD[8..0]
DATAOUT
ADVREFP
CLK[2..0]