Datasheet

485
32142D–06/2013
ATUC64/128/256L3/4U
20.8 Module Configuration
The specific configuration for each USART instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man-
ager chapter for details.
Table 20-19. USART Configuration
Feature USART0 USART1 USART2 USART3
Receiver Time-out Counter Size
(Size of the RTOR.TO field)
17 bit 17 bit 17 bit 17 bit
DIV Value for divided CLK_USART 8 8 8 8
Table 20-20. USART Clocks
Module Name Clock Name Description
USART0 CLK_USART0 Clock for the USART0 bus interface
USART1 CLK_USART1 Clock for the USART1 bus interface
USART2 CLK_USART2 Clock for the USART2 bus interface
USART3 CLK_USART3 Clock for the USART3 bus interface
Table 20-21. Register Reset Values
Register Reset Value
VERSION 0x00000440