Datasheet

458
32142D–06/2013
ATUC64/128/256L3/4U
Figure 20-30. Slave Node Configuration, NACT=PUBLISH
Figure 20-31. Slave Node Configuration, NACT=SUBSCRIBE
Figure 20-32. Slave Node Configuration, NACT=IGNORE
20.6.8 LIN Frame Handling With The Peripheral DMA Controller
The USART can be used together with the Peripheral DMA Controller in order to transfer data
without processor intervention. The DMA Controller uses the TXRDY and RXRDY bits, to trigger
one byte writes or reads. It always writes to THR, and it always reads RHR.
Break Synch Protected
Identifier
Data 1 Data N Checksum
TXRDY
Write
THR
Read
LINID
Data 1 Data 3
Data N-1
Data N
RXRDY
LINIDRX
Data 2
LINTC
TXRDY
Read
RHR
Read
LINID
RXRDY
LINIDRX
LINTC
Break Synch Protected
Identifier
Data 1 Data N Checksum
Data 1
Data N-1
Data N-1 Data NData N-2
TXRDY
Read
RHR
Read
LINID
RXRDY
LINIDRX
LINTC
Break Synch Protected
Identifier
Data 1 Data N ChecksumData N-1