Datasheet

448
32142D–06/2013
ATUC64/128/256L3/4U
• The Clock Selection field (MR.USCLKS) must not equal 0x3 (external clock, CLK).
• The Clock Output Select bit (MR.CLKO) must be one.
• The BRGR.CD field must be at least 0x4.
• If USCLKS is one (internal divided clock, CLK_USART/DIV), the value in CD has to be even,
ensuring a 50:50 duty cycle. CD can be odd if USCLKS is zero (internal clock, CLK_USART).
In SPI Slave Mode:
• CLK frequency must be at least four times lower than the system clock.
20.6.4.3 Data Transfer
• Up to nine data bits are successively shifted out on the TXD pin at each edge. There are no
start, parity, or stop bits, and MSB is always sent first. The SPI Clock Polarity (MR.CPOL),
and SPI Clock Phase (MR.CPHA) bits configure CLK by selecting the edges upon which bits
are shifted and sampled, resulting in four non-interoperable protocol modes see Table 20-7.
A master/slave pair must use the same configuration, and the master must be reconfigured if
it is to communicate with slaves using different configurations. See Figures 20-19 and 20-20.
Figure 20-19. SPI Transfer Format (CPHA=1, 8 bits per transfer)
Table 20-7. SPI Bus Protocol Modes
SPI Bus Protocol Mode CPOL CPHA
001
100
211
310
CLK cycle (for reference)
CLK
(CPOL= 1)
MOSI
SPI Master ->TXD
SPI Slave ->RXD
MISO
SPI Master ->RXD
SPI Slave ->TXD
NSS
SPI Master ->RTS
SPI Slave ->CTS
MSB
MSB
1
CLK
(CPOL= 0)
3
5
6
78
LSB
1234
6
65
5
43
21
LSB
24