Datasheet

446
32142D–06/2013
ATUC64/128/256L3/4U
Figure 20-14. Break Transmission
20.6.3.11 Receive Break
A break condition is assumed when incoming data, parity, and stop bits are zero. This corre-
sponds to a framing error, but FRAME will remain zero while the Break Received/End Of Break
bit (CSR.RXBRK) is set. Writing a one to CR.RSTSTA will clear RXBRK. An end of break will
also set RXBRK, and is assumed when TX is high for at least 2/16 of a bit period in asynchro-
nous mode, or when a high level is sampled in synchronous mode.
20.6.3.12 Hardware Handshaking
The USART features an out-of-band hardware handshaking flow control mechanism, imple-
mentable by connecting the RTS and CTS pins with the remote device, as shown in Figure 20-
15.
Figure 20-15. Connection with a Remote Device for Hardware Handshaking
Writing 0x2 to the MR.MODE field configures the USART to operate in this mode. The receiver
will drive its RTS pin high when disabled or when the Reception Buffer Full bit (CSR.RXBUFF) is
set by the Buffer Full signal from the Peripheral DMA controller. If the receivers RTS pin is high,
the transmitters CTS pin will also be high and only the active character transactions will be com-
pleted. Allocating a new buffer to the DMA controller by clearing RXBUFF, will drive the RTS pin
low, allowing the transmitter to resume transmission. Detected level changes on the CTS pin
can trigger interrupts, and are reported by the CTS Input Change bit in the Channel Status Reg-
ister (CSR.CTSIC).
Figure 20-16 illustrates receiver functionality, and Figure 20-17 illustrates transmitter
functionality.
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit
Parity
Bit
Stop
Bit
Baud Rate
Clock
Write
CR
TXRDY
TXEMPTY
STPBRK = 1
STTBRK = 1
Break Transmission End of Break
USART
TXD
CTS
Remote
Device
RXD
TXDRXD
RTS
RTS
CTS