Datasheet

401

32142D–06/2013

ATUC64/128/256L3/4U

18.7 Module Configuration

The specific configuration for each FREQM instance is listed in the following tables. The module

bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man-

ager chapter for details.

Table 18-2. FREQM Clock Name

Module Name Clock Name Description

FREQM

CLK_FREQM Bus interface clock

CLK_MSR Measured clock

CLK_REF Reference clock

Table 18-3. Register Reset Values

VERSION 0x00000310

Table 18-4. Clock Sources for CLK_MSR

CLKSEL Clock/Oscillator Description

0 CLK_CPU The clock the CPU runs on

1 CLK_HSB High Speed Bus clock

2 CLK_PBA Peripheral Bus A clock

3 CLK_PBB Peripheral Bus B clock

4 OSC0 Output clock from Oscillator 0

5 OSC32K Output clock from OSC32K

6 RCSYS Output clock from RCSYS Oscillator

7 DFLL0 Output clock from DFLL0

8 Reserved

9-18 GCLK0-9 Generic clock 0 through 9

19 RC120M AW clock Output clock from RC120M to AW

20 RC120M Output clock from RC120M to main clock mux

21 RC32K Output clock from RC32K

22-31 Reserved

Table 18-5. Clock Sources for CLK_REF

REFSEL Clock/Oscillator Description

0 RCSYS System RC oscillator clock