Datasheet

320
32142D–06/2013
ATUC64/128/256L3/4U
.
Table 14-12. PLL Clock Sources
PLLOSC Clock/Oscillator Description
0 OSC0 Output clock from Oscillator0
1 GCLK8 Generic clock 8
2-3 Reserved
Table 14-13. Generic Clock number of DIV bits
Generic Clock Number of DIV bits
08
18
28
38
48
58
68
78
88
916
Table 14-14. Register Reset Values
Register Reset Value
CMVERSION 0x00000100
PLLVERSION 0x00000110
OSC0VERSION 0x00000111
OSC32VERSION 0x00000110
DFLLIFVERSION 0x00000210
BODIFAVERSION 0x00000120
VREGIFBVERSION 0x00000110
RCOSCIFAVERSION 0x00000111
SM33IFAVERSION 0x00000110
TSENSEIFAVERSION 0x00000100
RC120MIFAVERSION 0x00000110
BRIFAVERSION 0x00000100