Datasheet

319
32142D–06/2013
ATUC64/128/256L3/4U
In ATUC64/128/256L3/4U, there are 10 generic clocks. These are allocated to different func-
tions as shown in Table 14-10.
Table 14-10. Generic Clock Allocation
Clock number Function
0
DFLLIF main reference and GCLK0 pin
(CLK_DFLLIF_REF)
1
DFLLIF dithering and SSG reference and GCLK1 pin
(CLK_DFLLIF_DITHER)
2 AST and GCLK2 pin
3 PWMA and GCLK3 pin
4 CAT, ACIFB and GCLK4 pin
5 GLOC and GCLK5 pin
6 ABDACB, IISC, and GCLK6 pin
7 USBC and GCLK7 pin
8 PLL0 source clock and GCLK8 pin
9
Master generic clock and GCLK9 pin. Can be used as
source for other generic clocks.
Table 14-11. Generic Clock Sources
OSCSEL Clock/Oscillator Description
0 RCSYS System RC oscillator clock
1 OSC32K Output clock from OSC32K
2 DFLL0 Output clock from DFLL0
3 OSC0 Output clock from Oscillator0
4 RC120M Output from 120MHz RCOSC
5 CLK_CPU The clock the CPU runs on
6 CLK_HSB High Speed Bus clock
7 CLK_PBA Peripheral Bus A clock
8 CLK_PBB Peripheral Bus B clock
9 RC32K Output from 32KHz RCOSC
10 Reserved
11 CLK_1K 1KHz output clock from OSC32K
12 PLL0 Output clock from PLL0
13-14 Reserved
15-17 GCLK_IN[0-2] GCLK_IN[0-2] pins, digital clock input
18 GCLK9
Generic clock 9. Can not be used as
an input to itself
19-31 Reserved