Datasheet

297
32142D–06/2013
ATUC64/128/256L3/4U
• PLLEN: PLL Enable
0: PLL is disabled.
1: PLL is enabled.
Note that it is not possible to change any of the PLL configuration bits when the PLL is enabled, Any write to PLLn while the PLL
is enabled will be discarded.
Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please
refer to the UNLOCK register description for details.