Datasheet

296
32142D–06/2013
ATUC64/128/256L3/4U
14.6.25 PLL Control Register
Name:
PLLn
Access Type: Read/Write
Reset Value: 0x00000000
• PLLCOUNT: PLL Count
Specifies the number of RCSYS clock cycles before ISR.PLLLOCKn will be set after PLLn has been written, or after PLLn has
been automatically re-enabled after exiting a sleep mode.
• PLLMUL: PLL Multiply Factor
• PLLDIV: PLL Division Factor
These fields determine the ratio of the PLL output frequency to the source oscillator frequency:
f
vco
= (PLLMUL+1)/PLLDIV • f
REF
if PLLDIV >0
f
vco
= 2•(PLLMUL+1) • f
REF
if PLLDIV = 0
Note that the PLLMUL field should always be greater than 1 or the behavior of the PLL will be undefined.
• PLLOPT: PLL Option
PLLOPT[0]: Selects the VCO frequency range (f
vco
).
0: 80MHz<f
vco
<180MHz
1: 160MHz<f
vco
<240MHz
PLLOPT[1]: Divides the output frequency by 2.
0: f
PLL
= f
vco
1: f
PLL
= f
vco
/2
PLLOPT[2]:Wide-Bandwidth mode.
0: Wide Bandwidth Mode enabled
1: Wide Bandwidth Mode disabled
• PLLOSC: PLL Oscillator Select
Reference clock source select for the reference clock, please refer to the “PLL Clock Sources” table in the SCIF
Module Configuration section for details.
31 30 29 28 27 26 25 24
- - PLLCOUNT
23 22 21 20 19 18 17 16
---- PLLMUL
15 14 13 12 11 10 9 8
---- PLLDIV
76543210
- - PLLOPT PLLOSC PLLEN