Datasheet

264
32142D–06/2013
ATUC64/128/256L3/4U
• PLLLOCK - PLL Lock
– A 0 to 1 transition on the PCLKSR.PLLLOCK bit is detected.
• PLLLOCKLOST - PLL Lock Lost
– A to 1 transition on the PCLKSR.PLLLOCKLOST bit is detected.
• BRIFARDY - Backup Register Interface Ready.
– A 0 to 1 transition on the PCLKSR.BRIFARDY bit is detected.
• DFLL0RCS - DFLL Reference Clock Stopped:
– A 0 to 1 transition on the PCLKSR.DFLLRCS bit is detected.
• DFLL0RDY - DFLL Ready:
– A 0 to 1 transition on the PCLKSR.DFLLRDY bit is detected.
• DFLL0LOCKLOSTA - DFLL lock lost on Accurate value:
– A 0 to 1 transition on the PCLKSR.DFLLLOCKLOSTA bit is detected.
• DFLL0LOCKLOSTF - DFLL lock lost on Fine value:
– A 0 to 1 transition on the PCLKSR.DFLLLOCKLOSTF bit is detected.
• DFLL0LOCKLOSTC - DFLL lock lost on Coarse value:
– A 0 to 1 transition on the PCLKSR.DFLLLOCKLOSTC bit is detected.
• DFLL0LOCKA - DFLL Locked on Accurate value:
– A 0 to 1 transition on the PCLKSR.DFLLLOCKA bit is detected.
• DFLL0LOCKF - DFLL Locked on Fine value:
– A 0 to 1 transition on the PCLKSR.DFLLLOCKF bit is detected.
• DFLL0LOCKC - DFLL Locked on Coarse value:
– A 0 to 1 transition on the PCLKSR.DFLLLOCKC bit is detected.
• BODDET - Brown out detection:
– A 0 to 1 transition on the PCLKSR.BODDET bit is detected.
• SM33DET - Supply Monitor 3.3V Detector:
– A 0 to 1 transition on the PCLKSR.SM33DET bit is detected.
• VREGOK - Voltage Regulator OK:
– A 0 to 1 transition on the PCLKSR.VREGOK bit is detected.
• OSC0RDY - Oscillator Ready:
– A 0 to 1 transition on the PCLKSR.OSC0RDY bit is detected.
• OSC32RDY - 32KHz Oscillator Ready:
– A 0 to 1 transition on the PCLKSR.OSC32RDY bit is detected.
The interrupt sources will generate an interrupt request if the corresponding bit in the Interrupt
Mask Register is set. The interrupt sources are ORed together to form one interrupt request. The
SCIF will generate an interrupt request if at least one of the bits in the Interrupt Mask Register
(IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable
Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable
Register (IDR). The interrupt request remains active until the corresponding bit in the Interrupt
Status Register (ISR) is cleared by writing a one to the corresponding bit in the Interrupt Clear
Register (ICR). Because all the interrupt sources are ORed together, the interrupt request from
the SCIF will remain active until all the bits in ISR are cleared.