Datasheet

258
32142D–06/2013
ATUC64/128/256L3/4U
synchronisation, the masking is not immediately effective, so software should wait for the
VREGCR.POR18MASK to read as one before assuming the masking is effective.
The output of the POR18 detector is zero if the VDDCORE voltage is below the POR18 power-
on threshold level, and one if the VDDCORE voltage is above the POR18 power-on threshold
level. The output of the POR18 detector (before masking) can be read from the POR18 Value bit
(VREGCR.POR18VALUE).
14.5.9 3.3 V Supply Monitor (SM33)
Rev: 1.1.0.0
The 3.3V supply monitor is a specific voltage detector for the internal regulator supply voltage. It
will indicate if the internal regulator supply voltage is above the minimum required input voltage
threshold. The user can choose to generate either a Power-on Reset (POR) and an interrupt
request, or only an interrupt request, when the internal regulator supply voltage drops below this
threshold.
Please refer to the Electrical Characteristics chapter for parametric details.
14.5.9.1 Register protection
To prevent unexpected writes to SM33 register due to software bugs, write access to this regis-
ter is protected by a locking mechanism. For details please refer to the UNLOCK register
description.
To prevent further modifications by software, the content of the register can be set as read-only
by writing a one to the Store Final Value bit (SM33.SFV). When this bit is one, software can not
change the SM33 register content until the device is reset.
14.5.9.2 Operating modes
The SM33 is disabled by default and is enabled by writing to the Supply Monitor Control field in
the SM33 control register (SM33.CTRL). The current state of the SM33 can be read from the
Supply Monitor On Indicator bit in SM33 (SM33.ONSM). Enabling the SM33 will disable the
POR33 detector.
The SM33 can operate in continuous mode or in sampling mode. In sampling mode, the SM33 is
periodically enabled for a short period of time, just enough to make a a measurement, and then
disabled for a longer time to reduce power consumption.
By default, the SM33 operates in sampling mode during DeepStop and Static mode and in con-
tinuous mode for other sleep modes. Sampling mode can also be forced during sleep modes
other than DeepStop and Static, and during normal operation, by writing a one to the Force
Sampling Mode bit in the SM33 register (SM33.FS).
The user can select the sampling frequency by writing to the Sampling Frequency field in SM33
(SM33.SAMPFREQ). The sampling mode uses the 32kHz RC oscillator (RC32K) as clock
source. The 32kHz RC oscillator is automatically enabled when the SM33 operates in sampling
mode.
14.5.9.3 Interrupt and reset generation
If the SM33 is enabled (SM33.CTRL is one or two) and the regulator supply voltage drops below
the SM33 threshold, the SM33DET bit in the Power and Clocks Status Register
(PCLKSR.SM33DET) is set. This bit is cleared when the supply voltage goes above the thresh-
old. An interrupt request is generated on a zer-to-one transition of PCLKSR.SM33DET if the