Datasheet

252
32142D–06/2013
ATUC64/128/256L3/4U
Drift compensation
The frequency tuner will automatically compensate for drift in the f
DFLL
without losing either of the
locks. If the FINE value overflows or underflows, which should normally not happen, but could
occur due to large drift in temperature and voltage, all locks will be lost, and the COARSE and
FINE values will be recalibrated as described earlier. If any lock is lost the corresponding bit in
PCLKSR will be set, DFLLn Lock Lost on Coarse Value bit (DFLLnLOCKLOSTC) for lock lost on
COARSE value, DFLLn Lock Lost on Fine Value bit (DFLLnLOCKLOSTF) for lock lost on FINE
value and DFLLn Lock Lost on Accurate Value bit (DFLLnLOCKLOSTA) for lock lost on ACCU-
RATE value. The corresponding lock status bit will be cleared when the lock lost bit is set, and
vice versa.
Reference clock stop detection
If CLK_DFLLIF_REF stops or is running at a very slow frequency, the DFLLn Reference Clock
Stopped bit (DFLLnRCS) in PCLKSR will be set. Note that the detection of the clock stop will
take a long time. The DFLLIF operate as if it was in open loop mode if it detects that the refer-
ence clock has stopped. This means that the COARSE and FINE values will be kept constant
while PCLKSR.DFLLnRCS is set. Closed loop mode operation will automatically resume if the
CLK_DFLLIF_REF is restarted, and compensate for any drift during the time CLK_DFLLIF_REF
was stopped. No locks will be lost.
Frequency error measurement
The ratio between CLK_DFLLIF_REF and CLK_DFLL is measured automatically by the DFLLIF.
The difference between this ratio and DFLLnMUL is stored in the Multiplication Ratio Difference
field (RATIODIFF) in the DFLLn Ratio Register (DFLLnRATIO). The relative error on CLK_DFLL
compared to the target frequency can be calculated as follows:
where is the number of reference clock cycles the DFLLIF is using for calculating the
ratio.
14.5.4.6 Dealing with delay in the DFLL
The time from selecting a new frequency until this frequency is output by the DFLL, can be up to
several micro seconds. If the difference between the desired output frequency (CLK_DFLL) and
the frequency of CLK_DFLLIF_REF is small this can lead to an instability in the DFLLIF locking
mechanism, which can prevent the DFLLIF from achieving locks. To avoid this, a chill cycle
where the CLK_DFLL frequency is not measured can be enabled. The chill cycle is enabled by
writing a one to the Chill Cycle Enable (CCEN) bit in the DFLLnCONF register. Enabling chill
cycles might double the lock time,
Another solution to the same problem can be to use less strict lock requirements. This is called
Quick Lock (QL), which is enabled by writing a one to the Quick Lock Enable (QLEN) bit in the
DFLLnCONF register. The QL might lead to bigger spread in the outputted frequency than chill
cycles, but the average output frequency is the same.
If the target frequency is below 40MHz, one of these methods should always be used.
14.5.4.7 Spread Spectrum Generator (SSG)
When the DFLL is used as the main clock source for the device, the EMI radiated from the
device will be synchronous to f
DFLL
. To provide better Electromagnetic Compatibility (EMC) the
error
RATIODIFF f
REF

2
NUMREF
f
DFLL

------------------------------------------------ -=
2
NUMREF