Datasheet

251
32142D–06/2013
ATUC64/128/256L3/4U
only be executed if the Dithering Enable bit (DITHER) in DFLLnCONF has been written to a one.
If DITHER is written to a zero DFLLnLOCKA will never occur. If dithering is enabled, the fre-
quency of the dithering is decided by a generic clock (CLK_DFLLIF_DITHER). This clock has to
be set up correctly before enabling dithering. Please refer to the Generic Clocks section for
details.
Figure 14-3. DFLL Closed loop State Diagram
When dithering is enabled the accuracy of the average output frequency of the DFLL will be
higher. However, the actual frequency will be alternating between two frequencies. If a fixed fre-
quency is required, the dithering should not be enabled.
Figure 14-4. DFLL Locking in Closed loop
CLK_DFLL is ready to be used when the DFLLn Synchronization Ready bit (DFLLnRDY) in
PCLKSR is set after enabling the DFLL. However, the accuracy of the output frequency depends
on which locks are set.
For lock times, please refer to the Electrical Characteristics chapter.
Measure
f
DFLLn
Calculate
new
COARSE
value
DFLLnLOCKC
0
Calculate
new FINE
value
DFLLnLOCKF
0
1 DFLLnLOCKA1
Calculate
new
dithering
dutycycle
0
Compen-
sate for
drift
1DITHER1
Compen-
sate for
drift
0
Initial
frequency
Target
frequency
DFLLnLOCKC
DFLLnLOCKF DFLLnLOCKA