Datasheet

243
32142D–06/2013
ATUC64/128/256L3/4U
13.8 Module Configuration
The specific configuration for each PM instance is listed in the following tables. The module bus
clocks listed here are connected to the system bus clocks. Please refer to the “Synchronous
Clocks”, “Peripheral Clock Masking” and “Sleep Modes” sections for details.
Table 13-14. Power Manager Clocks
Clock Name Description
CLK_PM Clock for the PM bus interface
Table 13-15. Register Reset Values
Register Reset Value
VERSION 0x00000420
Table 13-16. Effect of the Different Reset Events
Power-on
Reset
External
Reset
Watchdog
Reset
BOD
Reset
SM33
Reset
CPU Error
Reset
OCD
Reset
JTAG
Reset
CPU/HSB/PBx
(excluding Power Manager)
YYYYYYYY
32KHz oscillator Y N N N N N N N
RC Oscillator Calibration register Y N N N N N N N
Other oscillator control registers Y Y Y Y Y Y Y Y
AST registers, except interrupt
registers
YNNNNNNN
Watchdog control register Y Y N Y Y Y Y Y
Voltage Calibration register Y N N N N N N N
SM33 control register Y Y Y Y Y Y Y Y
BOD control register Y Y Y N Y Y Y Y
Clock control registers Y Y Y Y Y Y Y Y
OCD system and OCD registers Y Y N Y Y Y N Y