Datasheet

238
32142D–06/2013
ATUC64/128/256L3/4U
13.7.16 Reset Cause Register
Name:
RCAUSE
Access Type: Read-only
Offset: 0x180
Reset Value: Latest Reset Source
• AWIRE: aWire Reset
This bit is set when the last reset was caused by the aWire.
• JTAG: JTAG Reset
This bit is set when the last reset was caused by the JTAG.
• OCDRST: OCD Reset
This bit is set when the last reset was due to the RES bit in the OCD Development Control register having been written to one.
• SLEEP: Sleep Reset
This bit is set when the last reset was due to the device waking up from the Shutdown sleep mode.
• WDT: Watchdog Reset
This bit is set when the last reset was due to a watchdog time-out.
• EXT: External Reset Pin
This bit is set when the last reset was due to the RESET_N pin being pulled low.
• BOD: Brown-out Reset
This bit is set when the last reset was due to the core supply voltage being lower than the brown-out threshold level.
• POR: Power-on Reset
This bit is set when the last reset was due to the core supply voltage VDDCORE being lower than the power-on threshold level
(the reset is generated by the POR18 detector), or the internal regulator supply voltage being lower than the regulator power-on
threshold level (generated by the POR33 detector), or the internal regulator supply voltage being lower than the minimum
required input voltage (generated by the 3.3V supply monitor SM33).
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
---AWIRE- JTAGOCDRST
76543210
-
SLEEP - - WDT EXT BOD POR