Datasheet

227
32142D–06/2013
ATUC64/128/256L3/4U
13.7.6 PBA Divided Mask
Name:
PBADIVMASK
Access Type: Read/Write
Offset: 0x040
Reset Value: 0x0000007F
• MASK: Clock Mask
If bit n is written to zero, the clock divided by 2
(n+1)
is stopped. If bit n is written to one, the clock divided by 2
(n+1)
is enabled
according to the current power mode. Table 13-10 shows what clocks are affected by the different MASK bits.
Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please
refer to the UNLOCK register description for details.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- ------
15 14 13 12 11 10 9 8
--------
76543210
- MASK[6:0]
Table 13-10. Divided Clock Mask
Bit USART0 USART1 USART2 USART3 TC0 TC1
0----TIMER_CLOCK2TIMER_CLOCK2
1---- - -
2
CLK_USART/
DIV
CLK_USART/
DIV
CLK_USART/
DIV
CLK_USART/
DIV
TIMER_CLOCK3 TIMER_CLOCK3
3---- - -
4----TIMER_CLOCK4TIMER_CLOCK4
5---- - -
6----TIMER_CLOCK5TIMER_CLOCK5