Datasheet

225
32142D–06/2013
ATUC64/128/256L3/4U
13.7.5 Clock Mask
Name:
CPUMASK/HSBMASK/PBAMASK/PBBMASK
Access Type: Read/Write
Offset: 0x020-0x02C
Reset Value: -
• MASK: Clock Mask
If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current
power mode. The number of implemented bits in each mask register, as well as which module clock is controlled by each bit, is
shown in Table 13-9.
31 30 29 28 27 26 25 24
MASK[31:24]
23 22 21 20 19 18 17 16
MASK[23:16]
15 14 13 12 11 10 9 8
MASK[15:8]
76543210
MASK[7:0]
Table 13-9. Maskable Module Clocks in ATUC64/128/256L3/4U.
Bit CPUMASK HSBMASK PBAMASK PBBMASK
0 OCD PDCA PDCA FLASHCDW
1 - FLASHCDW INTC HMATRIX
2- SAU PM SAU
3 - PBB bridge SCIF USBC
4 - PBA bridge AST -
5 - Peripheral Event System WDT -
6 - USBC EIC -
7- - FREQM -
8- - GPIO -
9 - - USART0 -
10 - - USART1 -
11 - - USART2 -