Datasheet

220
32142D–06/2013
ATUC64/128/256L3/4U
13.7 User Interface
Note: 1. The reset value is device specific. Please refer to the Module Configuration section at the end of this chapter.
2. Latest Reset Source.
3. Latest Wake Source.
Table 13-7. PM Register Memory Map
Offset Register Register Name Access Reset
0x000 Main Clock Control MCCTRL Read/Write 0x00000000
0x004 CPU Clock Select CPUSEL Read/Write 0x00000000
0x008 HSB Clock Select HSBSEL Read-only 0x00000000
0x00C PBA Clock Select PBASEL Read/Write 0x00000000
0x010 PBB Clock Select PBBSEL Read/Write 0x00000000
0x014 - 0x01C Reserved
0x020 CPU Mask CPUMASK Read/Write 0x00010001
0x024 HSB Mask HSBMASK Read/Write 0x0000007F
0x028 PBA Mask PBAMASK Read/Write 0x0FFFFFFF
0x02C PBB Mask PBBMASK Read/Write 0x0000000F
0x030- 0x03C Reserved
0x040 PBA Divided Mask PBADIVMASK Read/Write 0x0000007F
0x044 - 0x050 Reserved
0x054 Clock Failure Detector Control CFDCTRL Read/Write 0x00000000
0x058 Unlock Register UNLOCK Write-only 0x00000000
0x05C - 0x0BC Reserved
0x0C0 Interrupt Enable Register IER Write-only 0x00000000
0x0C4 Interrupt Disable Register IDR Write-only 0x00000000
0x0C8 Interrupt Mask Register IMR Read-only 0x00000000
0x0CC Interrupt Status Register ISR Read-only 0x00000000
0x0D0 Interrupt Clear Register ICR Write-only 0x00000000
0x0D4 Status Register SR Read-only 0x00000020
0x0D8 - 0x15C Reserved
0x160 Peripheral Power Control Register PPCR Read/Write 0x000001FA
0x164 - 0x17C Reserved
0x180 Reset Cause Register RCAUSE Read-only -
(2)
0x184 Wake Cause Register WCAUSE Read-only -
(3)
0x188 Asynchronous Wake Up Enable Register AWEN Read/Write 0x00000000
0x18C - 0x3F4 Reserved
0x3F8 Configuration Register CONFIG Read-only 0x00000043
0x3FC Version Register VERSION Read-only -
(1)