Datasheet

213
32142D–06/2013
ATUC64/128/256L3/4U
13.6.3.1 Entering and exiting sleep modes
The sleep instruction will halt the CPU and all modules belonging to the stopped clock domains.
The modules will be halted regardless of the bit settings in the mask registers.
Clock sources can also be switched off to save power. Some of these have a relatively long
start-up time, and are only switched off when very low power consumption is required.
The CPU and affected modules are restarted when the sleep mode is exited. This occurs when
an interrupt triggers. Note that even if an interrupt is enabled in sleep mode, it may not trigger if
the source module is not clocked.
13.6.3.2 Supported sleep modes
The following sleep modes are supported. These are detailed in Table 13-2 on page 213.
• Idle: The CPU is stopped, the rest of the device is operational.
• Frozen: The CPU and HSB modules are stopped, peripherals are operational.
• Standby: All synchronous clocks are stopped, and the clock sources are running, allowing for
a quick wake-up to normal mode.
• Stop: As Standby, but oscillators, and other clock sources are also stopped. 32KHz Oscillator
OSC32K
(2)
, RCSYS, AST, and WDT will remain operational.
• DeepStop: All synchronous clocks and clock sources are stopped. Bandgap voltage
reference and BOD are turned off. OSC32K
(2)
and RCSYS remain operational.
• Static: All clock sources, including RCSYS are stopped. Bandgap voltage reference and BOD
are turned off. OSC32K
(2)
remains operational.
• Shutdown: All clock sources, including RCSYS are stopped. Bandgap voltage reference,
BOD detector, and Voltage regulator are turned off. OSC32K
(2)
remains operational. This
mode can only be used in the “
3.3V supply mode, with 1.8V regulated I/O lines“
configuration (described in Power Considerations chapter). Refer to Section 13.6.4 for more
details.
Notes: 1. The sleep mode index is used as argument for the sleep instruction.
2. OSC32K will only remain operational if pre-enabled.
3. Clock sources other than those specifically listed in the table.
4. SYSTIMER is the clock for the CPU COUNT and COMPARE registers.
The internal voltage regulator is also adjusted according to the sleep mode in order to reduce its
power consumption.
Table 13-2. Sleep Modes
Index
(1)
Sleep Mode CPU HSB
PBx,
GCLK
Clock Sources
(3)
,
SYSTIMER
(4)
OSC32K
(2)
RCSYS
BOD &
Bandgap
Voltage
Regulator
0 Idle Stop Run Run Run Run Run On Normal mode
1 Frozen Stop Stop Run Run Run Run On Normal mode
2 Standby Stop Stop Stop Run Run Run On Normal mode
3 Stop Stop Stop Stop Stop Run Run On Low power mode
4 DeepStop Stop Stop Stop Stop Run Run Off Low power mode
5 Static Stop Stop Stop Stop Run Stop Off Low power mode
6 Shutdown Stop Stop Stop Stop Run Stop Off Off