Datasheet

210
32142D–06/2013
ATUC64/128/256L3/4U
13.3 Block Diagram
Figure 13-1. PM Block Diagram
13.4 I/O Lines Description
13.5 Product Dependencies
13.5.1 Interrupt
The PM interrupt line is connected to one of the interrupt controllers internal sources. Using the
PM interrupt requires the interrupt controller to be configured first.
13.5.2 Clock Implementation
In ATUC64/128/256L3/4U, the HSB shares source clock with the CPU. Write attempts to the
HSB Clock Select register (HSBSEL) will be ignored, and it will always read the same as the
CPU Clock Select register (CPUSEL).
The PM bus interface clock (CLK_PM) is generated by the Power Manager. This clock is
enabled at reset, and can be disabled in the Power Manager. If disabled it can only be re-
enabled by a reset.
13.5.3 Power Considerations
The Shutdown mode is only available for the “3.3V supply mode, with 1.8V regulated I/O lines“
power configuration.
Table 13-1. I/O Lines Description
Name Description Type Active Level
RESET_N Reset Input Low
Sleep Controller
Synchronous
Clock Generator
Reset Controller
Main Clock Sources
Sleep
Instruction
Power-on Reset
Detector(s)
Resets
Synchronous
clocks
CPU, HSB,
PBx
Interrupts
External Reset Pin
Reset Sources