Datasheet

206
32142D–06/2013
ATUC64/128/256L3/4U
12.7 Module Configuration
The specific configuration for each INTC instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man-
ager chapter for details.
12.7.1 Interrupt Request Signal Map
12.8 Interrupt Request Signal Map
The various modules may output Interrupt request signals. These signals are routed to the Inter-
rupt Controller (INTC), described in a later chapter. The Interrupt Controller supports up to 64
groups of interrupt requests. Each group can have up to 32 interrupt request signals. All interrupt
signals in the same group share the same autovector address and priority level. Refer to the
documentation for the individual submodules for a description of the semantics of the different
interrupt requests.
The interrupt request signals are connected to the INTC as follows.
Table 12-2. INTC Clock Name
Module Name Clock Name Description
INTC CLK_INTC Clock for the INTC bus interface
Table 12-3. Interrupt Request Signal Map
Group Line Module Signal
0 0 AVR32UC3 CPU SYSREG COMPARE
1
0 AVR32UC3 CPU OCD DCEMU_DIRTY
1 AVR32UC3 CPU OCD DCCPU_READ
2 0 Flash Controller FLASHCDW
3 0 Secure Access Unit SAU
4
0 Peripheral DMA Controller PDCA 0
1 Peripheral DMA Controller PDCA 1
2 Peripheral DMA Controller PDCA 2
3 Peripheral DMA Controller PDCA 3
5
0 Peripheral DMA Controller PDCA 4
1 Peripheral DMA Controller PDCA 5
2 Peripheral DMA Controller PDCA 6
3 Peripheral DMA Controller PDCA 7
6
0 Peripheral DMA Controller PDCA 8
1 Peripheral DMA Controller PDCA 9
2 Peripheral DMA Controller PDCA 10
3 Peripheral DMA Controller PDCA 11
7 0 Power Manager PM